1. Field of the Invention
The present invention relates to a nonvolatile ferroelectric memory device, and more particularly, to a sense amplifier for a nonvolatile ferroelectric memory device.
2. Background of the Related Art
Generally, a nonvolatile ferroelectric memory, i.e., a ferroelectric random access memory (FRAM) has a data processing speed equal to a dynamic random access memory (DRAM) and retains data even in power off. For this reason, the nonvolatile ferroelectric memory has received much attention as a next generation memory device.
The FRAM and DRAM are memory devices with similar structures, but the FRAM includes a ferroelectric capacitor having a high residual polarization characteristic. The residual polarization characteristic permits data to be maintained even if an electric field is removed.
FIG. 1 shows hysteresis loop of a general ferroelectric. As shown in FIG. 1, even if polarization induced by the electric field has the electric field removed, data is maintained at a certain amount (i.e., d and a states) without being erased due to the presence of residual polarization (or spontaneous polarization). A nonvolatile ferroelectric memory cell is used as a memory device by corresponding the d and a states to 1 and 0, respectively.
A related art nonvolatile ferroelectric memory device will now be described. FIG. 2 shows unit cell of a related art nonvolatile ferroelectric memory.
As shown in FIG. 2, the related art nonvolatile ferroelectric memory includes a bitline B/L formed in one direction, a wordline W/L formed to cross the bitline, a plate line P/L spaced apart from the wordline in the same direction as the wordline, a transistor T1 with a gate connected with the wordline and a source connected with the bitline, and a ferroelectric capacitor FC1. A first terminal of the ferroelectric capacitor FC1 is connected with a drain of the transistor T1 and second terminal is connected with the plate line P/L.
The data input/output operation of the related art nonvolatile ferroelectric memory device will now be described. FIG. 3a is a timing chart illustrating the operation of the write mode of the related art nonvolatile ferroelectric memory device, and FIG. 3b is a timing chart illustrating the operation of read mode thereof.
During the write mode, an externally applied chip enable signal CSBpad is activated from high state to low state. At the same time, if a write enable signal WEBpad is applied from high state to low state, the write mode starts. Subsequently, if address decoding in the write mode starts, a pulse applied to a corresponding wordline is transited from low state to high state to select a cell.
A high signal in a certain period and a low signal in a certain period are sequentially applied to a corresponding plate line in a period where the wordline is maintained at high state. To write a logic value "1" or "0" in the selected cell, a high signal or low signal synchronized with the write enable signal WEBpad is applied to a corresponding bitline.
In other words, a high signal is applied to the bitline, and if the low signal is applied to the plate line in a period where the signal applied to the wordline is high, a logic value "1" is written in the ferroelectric capacitor. A low signal is applied to the bitline, and if the signal applied to the plate line is high, a logic value "0" is written in the ferroelectric capacitor.
With reference to FIG. 3b, the reading operation of data stored in a cell by the above operation of the write mode will now be described. If an externally applied chip enable signal CSBpad is activated from high state to low state, all of bitlines become equipotential to low voltage by an equalizer signal EQ before a corresponding wordline is selected.
Then, the respective bitline becomes inactive and an address is decoded. The low signal is transited to the high signal in the corresponding wordline according to the decoded address so that a corresponding cell is selected.
The high signal is applied to the plate line of the selected cell to destroy data corresponding to the logic value "1" stored in the ferroelectric memory. If the logic value "0" is stored in the ferroelectric memory, the corresponding data is not destroyed.
The destroyed data and the data that is not destroyed are output as different values by the ferroelectric hysteresis loop, so that a sensing amplifier senses the logic value "1" or "0". In other words, if the data is destroyed, the "d" state is transited to an "f" state as shown in hysteresis loop of FIG. 1. If the data is not destroyed, "a" state is transited to the "f" state. Thus, if the sensing amplifier is enabled after a set time has elapsed, the logic value "1" is output in case that the data is destroyed while the logic value "0" is output in case that the data is not destroyed.
As described above, after the sensing amplifier outputs data, to recover the data to the original data, the plate line becomes inactive from high state to low state at the state that the high signal is applied to the corresponding wordline.
FIG. 4 is a block diagram showing the related art nonvolatile ferroelectric memory device having a cell structure of 1T/1C. As shown in FIG. 4, the related art nonvolatile ferroelectric memory device includes a main cell array 41, a reference cell array 42 assigned on a lower part of the main cell array 41, a wordline driver 43 formed at a side of the main cell array for applying a driving signal to the main cell array 41 and the reference cell array 42, and a sensing amplifier 44 formed at a lower part of the reference cell array 42.
The wordline driver 43 applies the driving signal to a main wordline of the main cell array 41 and a reference wordline of the reference cell array 42. The sensing amplifier 44 includes a plurality of sensing amplifiers and amplifies signals of a corresponding bitline B/L and bit bar line BB/L.
The operation of the related art nonvolatile ferroelectric memory device will now be described with reference to FIG. 5. FIG. 5 is a partially detailed view of FIG. 4. As shown in the drawing, the main cell array has a folded bitline structure in the same manner as DRAM.
Also, the reference cell array 42 has a folded bitline structure and includes a reference cell wordline and a reference cell plate line in pairs. At this time, reference cell wordline and the reference cell plate line pairs are defined as RWL_1 and RPL_1, and RWL_2 and RPL_2, respectively.
When the main cell wordline MWL_N-1 and the main cell plate line MPL_N-1 are activated, the reference cell wordline RWL_1 and the reference cell plate line RPL_1 are activated. Therefore, data in the main cell is loaded into the bitline B/L and data in the reference cell is loaded into the bit bar line BB/L.
When the main cell wordline MWL_N and the main cell plate line MPL_N are activated, the reference cell wordline RWL_2 and the reference cell plate line RPL_2 are activated. Therefore, data in the main cell is loaded into the bit bar line BB/L and data in the reference cell is loaded into the bitline B/L.
The reference voltage REF by the reference cell exists between the bitline levels B_H(high) and B_L(low) by the main cell. To generate the reference voltage REF between the bitline levels B_H and B_L, the logic value "1" or "0" may be stored in a capacitor of the reference cell. When the logic value "1" is stored in the capacitor of the reference cell, the size of the capacitor of the reference cell is smaller than that of the capacitor of the main cell. When the logic value "0" is stored in the capacitor of the reference cell, the size of the capacitor of the reference cell is greater than that of the capacitor of the main cell.
FIG. 6 is a diagram illustrating one of the plurality of sensing amplifiers constituting the sensing amplifier of FIG. 4. As shown in FIG. 6, the related art sensing amplifier has a structure of a latch type sensing amplifier.
In other words, the sensing amplifier in FIG. 6 includes two PMOS transistors and two NMOS transistors, and these PMOS and NMOS transistors have latch type inverter structures. The first PMOS transistor MP1 and the second PMOS transistor MP2 face each other. An output terminal of the first PMOS transistor MP1 is connected to a gate of the second PMOS transistor MP2, and an output terminal of the second PMOS transistor MP2 is connected to a gate of the first PMOS transistor MP1. An SAP signal is commonly applied to input terminals of the first and second PMOS transistors MP1 and MP2. The SAP signal is an active signal that activates the first and second PMOS transistors MP1 and MP2.
The first NMOS transistor MN1 is connected to the output terminal of the first PMOS transistor MP1 in series. The second NMOS transistor MN2 is connected to the output terminal of the second NMOS transistor MN2 in series. The output terminal of the second NMOS transistor MN2 is connected to a gate of the first NMOS transistor MN1, and the output terminal of the first NMOS transistor MN1 is connected to a gate of the second NMOS transistor MN2.
An SAN signal is commonly applied to input terminals of the first and second NMOS transistors MN1 and MN2. The SAN signal is an active signal that activates the first and second NMOS transistors MN1 and MN2.
The output terminals of the first PMOS transistor MP1 and first NMOS transistor MN1 are commonly connected to the bitline B_N. The output terminals of the second PMOS transistor MP2 and the second NMOS transistor MN2 are connected to the next bitline B_N+1.
The output of the sensing amplifier is respectively connected to the bitlines B_N and B_N+1 to be input and output to the main cell and the reference cell, respectively, thereby enabling input/output to the main cell and the reference cell.
The SAP signal, the SAN signal, and the signals of B_N and B_N+1 are all maintained at 1/2 Vcc for a precharge period when the sensing amplifier is not active. On the other hand, the SAP signal is pulled-up at high level and the SAN signal is pulled-down at low level.
FIG. 7 shows a system for sensing an upper cell array and a lower cell array using the related art sensing amplifier. The reference numeral `41a` denotes the upper cell array, and `41b` denotes the lower cell array. To sense data in the upper cell array, a TSEL signal, which is a control signal, is transited to a high level and a BSEL signal, which is a control signal, is transited to a low level. Accordingly, a path between the lower cell array and the sensing amplifier is blocked, and a path between the upper cell array and the sensing amplifier is opened. Then, the sensing amplifier senses the signal on the bit line and the bit bar line in the upper cell array.
To sense the data in the lower cell array, the TSEL signal is transited to a low level and the BSEL signal is transited to a high level. Accordingly, a path between the upper cell array and the sensing amplifier is blocked, and a path between the upper cell array and the sensing amplifier is opened. The sensing amplifier senses the signal of the bit line and the bit bar line of the lower cell array.
As described above, the related art nonvolatile ferroelectric memory device has various disadvantages. Since an input terminal of the sensing amplifier is directly connected to the upper and lower bit lines through a switching device, loads between the bit line and the bit bar line may differ. Accordingly, since an amplification may occur in a state of different loads, the amplification may become unstable.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.